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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH28S72PJG is 134,217,728 - word x 72-bit Sy nchronous DRAM stacked structural module. This consist of t hirty -six industry standard 64M x 4 Sy nchronous DRAMs in TSOP. The stacked structure of TSOP on a card edge dual inline package prov ides any application where high densities and large of quantities memory are required. This is a socket-ty pe memory m odule ,suitable f or easy interchange or addition of m odule.
85pin
1pin
FEATURES Frequency -5 -6 -7 133MHz 133MHz 100MHz CLK Access Time
(at Latch mode,Components)
94pin 95pin
10pin 11pin
5.4ns(CL=3) 5.4ns(CL=4) 6.0ns(CL=3)
124pin 40pin 41pin
Utilizes industry standard 64M X 4 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package , and industry standard PLL in TSSOP package. Single 3.3V +/- 0.3V supply Burst length 1/2/4/8/Full Page (programmable) Burst type sequential / interleave (programmable) Column access random Burst W rite / Single W rite (programmable) Auto precharge / Auto bank precharge controlled by A10 Auto refresh and Self refresh LVTTL Interface 8192 refresh cycles ev ery 64ms
125pin
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin
84pin
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 1
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PIN NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE0 DQMB0 DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0
PIN NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
PIN NAME VSS NC /S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD
PIN NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12
PIN NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
PIN NAME VSS CKE0 /S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
NC = No Connection
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add CKE0 /S0-3 DQM0-7 /W /RAS /CAS REGE Vdd
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CB0 CB1 CB2 CB3
D6 D24 D4 D22 D3 D21 D0
RCKE0 R/S0-3 RDQM0-7
D18
D1
D19
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB4 CB5 CB6 CB7
D9
D27
D10
D28
D2
D20
D11
D29
D12
D30
D13
D31
D5
D23
D14
D32
D15
D33
D7
D25
D16
D34
D8
D26
D17
D35
From PLL
CK0 CK1 - CK3 RCKE0 R/S0 R/S1 R/S2 R/S3
PLL Terminated
D0-35 D0-3,D8-12,D17 D18-21,D26-30,D35 D4-7,D13-16 D22-25,D31-34
SERIAL PD RDQM RDQM RDQM RDQM RDQM RDQM RDQM RDQM 0 1 2 3 4 5 6 7 SCL D0-1,D18-19 D2-3,D8,D20-21,D26WP A0 A1 A2 SDA
47K SA0 SA1 SA2 D4-5,D22-23 D6-7,D24-25 VDD D9-10,D27-28 D11-12,D17,D29-30,D35 VSS D13-14,D31-32 D15-16,D33-34
D0 to D35 D0 to D35
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 3
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0 Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When /S is high,any command means No Operation. Combination of /RAS,/CAS,/W defines basic commands. A0-12 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-12.The Column Address is specified by A0-9,A11.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA0,1 specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands
CKE0
Input
/S0 - 3 /RAS,/CAS,/W
Input
Input
A0-11
Input
BA0-1 DQ0-63 CB0-7 DQM0-7
Input
Input/Output Data In and Data out are referenced to the rising edge of CK Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
Input
Vdd,Vss REGE
Power Supply Power Supply for the memory mounted module. Output Register enable:When REGE is low,All control signals and address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode)
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 4
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH28S72PJG provides basic functions,bank(row)activate,burs t read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK /S /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Ref resh Option @ref resh command Precharge Option @precharge or read/write command def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 5
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Adress Entry & Bank Activate Single Bank Precharge Precharge All Bank Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRIT E CKE CKE n-1 n H H H H H H X X X X X X /S H L L L L L /RAS /CAS X H L L L H X H H H H L /WE BA0,1 X H H L L L X X V V X V A11 X X V X X V A10 A0-9 X X V L H L X X V X X V
WRITEA
H
X
L
H
L
L
V
V
H
V
READ
H
X
L
H
L
H
V
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
V X X X X X L
H X X X X X L
V X X X X X V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A11-12 = 0, A0-9 = Mode Address
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 6
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS /CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L L L L L H L L L L L H H L L L H L H L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 BA,RA BA,A10 X Op-Code, Mode-Add ACT PRE/PREA REFA MRS Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 7
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State WRIT E /S H L L L /RAS /CAS X H H H X H H L /WE X H L H X X BA BA,CA,A10 Address Command DESEL NOP TBST Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst
Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add
READ/READA ILLEGAL WRITE/ ILLEGAL WRITEA ACT Bank Active/ILLEGAL*2 PRE/PREA REFA MRS DESEL NOP TBST WRITE/ WRITEA ACT PRE/PREA REFA MRS ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
READ/READA ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 8
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 9
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add MRS ILLEGAL Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 10
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State SELF REFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /S X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend Action
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All banks idle State. 3. Must be legal command.
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 11
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before s tarting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burs t Length, Burst Type and /CAS Latency can be programmed by setting the mode regis ter(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CK /S BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 A6 0 A5 A4 A3 BT A2 A1 A0 BL /RAS /CAS LTMODE /WE BA0,1 A11-0 BL 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 BT= 0 1 2 4 8 R R R FP SEQUENTIAL INTERLEAVED
V
BT= 1 1 2 4 8 R R R R
CL 000 001 010 LATENCY MODE*1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH
101 110 111 BURST TYPE 0 1
WRIT E MODE
R:Reserved for Future Use FP: Full Page
*1:This v alue is f or components and buf f er mode, in case of latch mode(REGE="H"), 1 latency s hould be added
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 12
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK Command Address DQ CL= 3 BL= 4
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/CAS Latency
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 13
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 39 0 ~ 70 -45 ~ 100 Unit V V V mA W C C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted) Symbol Vdd Vss VIH VIL Parameter Supply Voltage Supply Voltage High-Level Input Voltage all inputs Low-Level Input Voltage all inputs Min. 3.0 0 2.0 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vdd+0.3 0.8 Unit V V V V
Note) 1:VIH(max)=5.5V f or pulse width less than 10ns. 2.VIL(min)=-1.0 f or pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CK pin Input Capacitance, I/O pin Test Condition @1MHz 1.4V bias 200mV swing Limits(max.) 25 25 35 22 Unit pF pF pF pF
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 14
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Parameter
operating current one bank activ e (discrete)
Symbol
Test Condition -5 tRC=min.tCLK=min, BL=1,CL=3 2745 369 351 1215 531 1395 855 2745 6795 423
Limits (max) -6 2385 369 351 1215 531 1395 855 2745 6795 423 -7 2050 286 286 970 394 1150 790 2230 6370 358
Unit mA mA mA mA mA mA mA mA mA mA
Icc1
precharge stanby current in power-down mode precharge stanby current in non power-down mode active stanby current in non power-down mode
one bank activ e (discrete)
Icc2P CKE=L, tCLK=Min Icc2PS CKE=CLK=L Icc2N CKE=H,tCLK=Min,/S=H Icc2NS CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed) Icc3N CKE=H,tCLK=Min,/S=H Icc3NS CKE=H,CLK=L tCLK=min, BL=4, CL=3,all banks activ e(discerte) Icc4 Icc5 tRC=min, tCLK=min Icc6 CKE <0.2V
burst current auto-refresh current self-refresh current
Note) 1:Icc(max) is specif ied at the output open condition. 2:Only 1phy sical bank is activ e f or Icc1,Icc4. 3:Both phy s ical bank are ref reshed at same time.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) IOZ VOH(AC) Ii VOL(AC) Limits Min. Max. Unit High-Level Output Voltage(DC) IOH=-2mA 2.4 V Low-Level Output Voltage(DC) IOL=2mA 0.4 V 20 uA Off-stare Output Current High-Level Output Voltage(AC) Q floating VO=0 ~ Vdd -20 CL=50pF, IOH=2 V -10 10 uA Input Current 2mA ~ Vdd+0.3V VIH=0 Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V Parameter Test Condition
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 15
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREM ENTS (Components)
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels : 0.8V to 2.0V Input Timing Measurement Level: 1.4V LATCH MODE -5 Min. Max. CL=3
CK cycle time CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Refresh cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time Average Refresh Interval time
Symbol Parameter
Limits -6 Min. Max. 10 7.5 2.5 2.5 1 1.5 0.8 67.5 75 20 45 20 15 15 15
-7 Min. 10 10 3 3 1 2 1 70 80 20 50 20 20 20 20 Max.
Unit
tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
7.5 7.5 2.5 2.5 1 1.5 0.8 60 60 15 45 15 15 15 15
ns ns ns ns 10 ns ns ns ns ns ns 120K ns ns ns ns ns 7.8 us
CL=4
10
10
120K
120K
7.8
7.8
CK
1.4V
Any AC timing is referenced to the input signal crossing through 1.4V.
Signal
1.4V
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 16
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE Limits Symbol Parameter CL=2 CL=3 tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Refresh cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time Average Refresh Interval time
-5 Min. Max. 7.5 7.5 2.5 2.5 1 6.5 0 60 60 15 45 15 15 15 15
-6 Min. Max. 10 7.5 2.5 2.5 1 6.5 0 67.5 75 20 45 20 15 15 15
-7 Min. 10 10 3 3 1 7 0 70 80 20 50 20 20 20 20 Max.
Unit
tCLK
CK cycle time
ns ns ns ns 10 ns ns ns ns ns ns 120K ns ns ns ns ns 7.8 us
10
10
120K
120K
7.8
7.8
SWITCHING CHARACTERISTICS (Components)
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) LATCH MODE Limits Symbol Parameter Min. tAC
Access time from CK
-5 Max. 5.4 5.4 3 3 0 CL=3 CL=4 3 3 5.4 5.4 3 3 0 3 3 Min. CL=3 CL=4
-6 Max. 6 5.4 3 3 0 6 5.4 3 3 Min.
-7 Max. 6 6
Unit ns ns ns ns ns
tOH
Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK
CL=3 CL=4
tOLZ tOHZ
6 6
ns ns
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 17
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE Symbol Parameter Min. tAC
Access time from CK
-5 Max. 5.4 5.4 3 3 0 CL=2 CL=3 3 3 5.4 5.4 CL=2 CL=3
Limits -6 Min. Max. 6 5.4 3 3 0 3 3 6 5.4
-7 Min. Max. 6 6 3 3 0 3 3 6 6
Unit ns ns ns ns ns ns ns
tOH
Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK
CL=2 CL=3
tOLZ
tOHZ
Note) 1 If c lock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VOUT 50pF
DQ 1.4V CK 1.4V
Output Timing Measurement Ref erence Point
CK
1.4V
DQ
tAC tOH
tOHZ
1.4V
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 18
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
tWR
CKE DQM A0-9
X
Y
X
Y
A10 A11
X
X
X
X
BA0,1 REGE DQ
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case 27/Mar. /2001 19
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP tRCD
/RAS
tRCD
/CAS
/WE
tWR tWR
CKE DQM A0-9
X X Y Y X X Y
A10 A11
X
X
X
X
X
X
X
X
BA0,1 REGE DQ
0
1
0
1
0
0
1
2
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 20
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Lacth mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE DQM A0-9
X
Y
X
Y
A10 A11 BA0,1 REGE
X
X
X
X
0
0
0
0
0
DQ
ACT#0
D0
D0
D0
D0
D0
D0
D0
D0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 21
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS /RAS
tRRD
tRRD
tRAS
tRP
tRCD
tRCD
/CAS /WE
tWR tWR
CKE DQM A0-9
X X Y Y X X Y
A10 A11 BA0,1 REGE
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
DQ
ACT#0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 22
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9
BL=4,CL=3,Buffer mode(REGE="L")
10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE CKE DQM
DQM read latency =2
A0-9
X
Y
X
Y
A10 A11
X
X
X
X
BA0,1 REGE
0
0
0
0
0
CL=3
DQ
ACT#0 READ#0
Q0
Q0
Q0
Q0
Q0
Q0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 23
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,CL=3,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS /RAS
tRRD tRAS tRCD tRP
tRRD
tRCD
/CAS /WE
CKE DQM
DQM read latency =2
A0-9
X
X
Y
Y
X
X
Y
A10 A11 BA0,1
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
REGE
CL=3 CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0
DQ
ACT#0 READ#0 ACT#1
PRE#0 READ#1
READ#0 ACT#0 PRE#1 ACT#2
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 24
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4, CL=3,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
CKE DQM
DQM read latency =3
A0-9
X
Y
X
Y
A10 A11 BA0,1 REGE
X
X
X
X
0
0
0
0
0
CL=3
DQ
ACT#0 READ#0
Q0
Q0
Q0
Q0
Q0
Q0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 25
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
0 1 2 3 4 5 6 7 8 9
BL=4,CL=3,Latch mode(REGE="H")
10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRAS tRP
tRRD
/RAS
tRCD tRCD
/CAS
/WE CKE DQM
DQM read latency =3
A0-9
X
X
Y
Y
X
X
Y
A10 A11
X
X
X
X
X
X
X
X
BA0,1
0
1
0
1
0
0
1
2
0
REGE
CL=3 CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0
DQ
ACT#0 READ#0 ACT#1
PRE#0 READ#1
READ#0 ACT#0 PRE#1 ACT#2
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 26
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE
CKE DQM A0-9
X X Y Y X Y X Y
A10 A11 BA0,1
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
REGE
DQ
ACT#0 ACT#1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 27
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE
CKE DQM A0-9
X X Y Y X Y X Y
A10 A11 BA0,1
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
REGE
DQ
ACT#0 ACT#1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 28
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL+tRP BL+tRP
/WE CKE DQM
DQM read latency =2
A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 REGE
0
1
0
1
0
0
1
1
CL=3
CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
DQ
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 29
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL+tRP BL+tRP
/WE CKE DQM
DQM read latency =3
A0-9 A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 REGE
0
1
0
1
0
0
1
1
CL=3
CL=3
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
DQ
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 30
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X X Y Y Y Y
X
X
X
X
BA0,1 REGE DQ
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 31
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X X Y Y Y Y
X
X
X
X
BA0,1 REGE DQ
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 32
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
1
0
CL=3
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
DQ
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 33
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 REGE
0
1
0
0
1
0
CL=3
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
DQ
ACT#0 READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 34
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS
/WE CKE DQM A0-9 A10 A11
X X Y Y Y Y Y
X
X
X
X
BA0,1 REGE
0
1
0
0
0
1
0
CL=3
DQ
D0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0 READ#0 WRITE#0 WRITE#0 WRITE#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 35
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS
/WE CKE DQM A0-9 A10 A11
X X Y Y Y Y Y
X
X
X
X
BA0,1 REGE
0
1
0
0
0
1
0
CL=3
DQ
D0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0 READ#0 WRITE#0 WRITE#0 WRITE#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001 36
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ REGE
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
ACT#0
READ#0 WRITE#0 READ#0 READ#0 READ#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
37
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ REGE
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
ACT#0
READ#0 WRITE#0 READ#0 READ#0 READ#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
38
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE
CKE DQM A0-9 A10 A11
X X Y Y X Y
X
X
X
X
X
X
BA0,1
0
1
0
1
0
1
1
1
DQ REGE
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
39
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X X Y Y X Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
40
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE
CKE DQM
DQM read latency=2
A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1
0
1
0
1
0
1
1
1
DQ REGE
ACT#0 READ#0 ACT#1
Q0
Q0
Q0
Q0
Q1
Q1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
41
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS
/WE CKE DQM
DQM read latency=3
A0-9 A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ REGE
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
42
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Se tting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRFC
tRSC
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
0 M X Y
X
X
BA0,1 DQ REGE
0
0
D0
D0
D0
D0
Auto-Ref (last of 8 cycles)
Mode Register Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
43
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Auto-Re fresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRFC
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X Y
X
X
BA0,1 DQ REGE
0
0
D0
D0
D0
D0
Auto-Refresh Before Auto-Refresh, all banks must be idle state.
ACT#0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
44
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Re fresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped tRFC
/CS
/RAS /CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM A0-9 A10 A11
X
X
X
BA0,1 DQ REGE
0
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
45
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X Y Y Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
46
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X Y Y Y
X
X
BA0,1 DQ REGE
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
47
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X Y Y Y
DQM read latency=2
X
X
BA0,1 DQ REGE
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
48
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE DQM A0-9 A10 A11
X Y Y Y
DQM read latency=3
X
X
BA0,1 DQ REGE
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
49
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
/RAS /CAS
/WE
Standby Power Down Active Power Down
CKE
CKE latency=1
DQM A0-9 A10 A11
X
X
X
BA0,1 DQ REGE
0
Precharge All
ACT#0
Italic parameter indicates minimum case MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
50
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Buffer mode(REGE="L")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE
CKE latency=1 CKE latency=1
DQM A0-9 A10 A11
X Y Y
X
X
BA0,1 DQ REGE
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
READ#0 WRITE#0 CLK suspended
CLK suspended Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
51
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10
BL=4,Latch mode(REGE="H")
11 12 13 14 15 16 17
CLK /CS
/RAS
tRCD
/CAS
/WE CKE
CKE latency=2 CKE latency=2
DQM A0-9 A10 A11
X Y Y
X
X
BA0,1 DQ REGE
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
READ#0 WRITE#0 CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
52
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -5,-6 -7 -5,-6 -7
SPD enrty data 128 256 Bytes SDRAM A0-A12 A0-A9,11 2BANK x72 0 LVTTL 7.5ns 10ns 5.4ns 6ns
ECC
SPD DATA(hex) 80 08 04 0D 0B 02 48 00 01 75 A0 54 60 02 82 04 04 01 8F 04 06 01 01 1F 0E 75 A0 A0 54 60 60 00 00 0F 14 0F 14 0F 14 2D 32
Cycle time for CL=3 SDRAM Access from Clock tAC for CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
self refresh(7.8uS) x4 x4 1 1/2/4/8/Full pag e 4bank 2/3 0 0
buffered,registered Precharge All,Auto precharge -5
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported # Banks on Each SDRAM device CAS# Latency CS# Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General
7.5ns 10ns 10ns 5.4ns 6ns 6ns N/A
23
SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2
-6 -7 -5
24
SDRAM Access form Clock(2nd highest CAS latency)
-6 -7
tAC for CL=2 25 26 27 28 SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum Row Active to Row Active Min.
-5 -6,-7, -5,-6 -7
N/A 15ns 20ns 15ns 20ns 15ns 20ns 45ns 50ns
29
RAS to CAS Delay Min
-5 -6,-7 -5.-6
30
Active to Precharge Min
-7
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
53
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31 32 33 Density of each bank on module Command and Address signal input setup time Command and Address signal input hold time
-5,-6 -7 -5,-6 -7
256MByte 1.5ns 2ns 0.8ns 1ns 1.5ns 2ns 0.8ns 1ns option JEDEC2 rev 1.2B Check sum for -5
80 15 20 08 10 15 20 08 10 00 02 12 EC 2D A4 1CFFFFFFFFFFFFFF 01 02 03 04
4D483238533732504A472D35202020202020 4D483238533732504A472D36202020202020 4D483238533732504A472D37202020202020
34 35 36-61 62
Data signal input setup time Data signal input hold time Superset Information (may be used in future) SPD Revision
-5,-6 -7 -5,-6 -7
-5,-6 -7
63
Checksum for bytes 0-62
Check sum for -6 Check sum for -7
64-71 72
Manufactures Jedec ID code per JEP-108E Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany MH28S72PJG-5
73-90
Manufactures Part Number
MH28S72PJG-6 MH28S72PJG-7
91-92 93-94 95-98 99-125 126
Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency
PCB revision year/week code serial number option 100MHz
rrrr yyww ssssssss 00 64
127 128+
Intel specification CAS# Latency support Unused storage locations
CL=2/3,AP,CK0 open
8F 00
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
54
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM EEPROM Components A.C. and D.C. Characteristics
Symbol VCC VSS VIH VIL VOL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Output Low Voltage Min. 3.0 0 Vddx0.7 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vccx0.3 0.4 Units V V V V V
EEPROM A.C.Timing Parameters (Ta=0 to 70C)
Symbol fSCL TI TAA TBUF Parameter SCL Clock Frequency Noise Supression Time Constant at SCL, SDA inputs SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New T ransmission Can Start
Limits Min. Max. 80 100 0.3 7.0 6.7 4.5 6.7 4.5 6.7 0 500 1 1 300 6.7 300 15
Units KHz ns us us us us us us us ns us ns us ns ms
THD:STA Start Condition Hold Time TLOW THIGH TSU:STA Clock Low Time Clock High Time Start Condition Setup Time
THD:DAT Data In Hold Time TSU:DAT TR TF Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time
TSU:STO Stop Condition Setup Time TDH TWR Data Out Hold Time Write Cycle Time
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TF TLOW
THIGH
TR
SCL
TSU:STA THD:STA THD:DAT
54
TSU:STO TSU:DAT
SDA IN
TAA TDH TBUF
SDA OUT
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
55
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35 3
8.89 11.43
6.35 36.83 24.495 42.18
6.35 54.61 127.35
1.27
3
43.18
6.5 Max
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
56
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-406-0.2
MITSUBISHI ELECTRIC
27/Mar. /2001
57

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